The SpacemiT V100 they claim is the first chip fully compliant with the RISC-V server specification. The SpacemiT V100 features a 46-core hybrid micro-architecture and can support up to two sockets per server for a total of 92 cores.

The hybrid micro-architecture comes from this 46-core chip packing 6 XiangShan Kunminghu V2R2 cores and then 40 SpacemiT X100 cores. The clock speeds are 2.2GHz to 2.4GHz, the CPU is manufactured on a 12nm process and features a 120 Watt TDP. This server-class CPU supports eight channel DDR5-4800 memory and PCIe 5.0 with 52 lanes.

The SpacemiT V100 supports the RISC-V server specification, including UEFI, ACPI, SMBIOS support, and more.

The SpacemiT V100 is interesting and promising from a RISC-V perspective at least granted a 46-core, 12nm, 52 lane PCIe 5.0, DDR5-4800 server processor in 2026+ selling on the "AI" boom isn't as advanced as Intel Xeon and AMD EPYC x86_64 processors or even Arm server CPUs. In any case it should be interesting to see the SpacemiT V100 performance for RISC-V class hardware and hopefully we'll find some hardware in the lab for benchmarking.

More details on the V100 can be found at SpacemiT.com. (https://www.spacemit.com/products/keystone/v100)

SpacemiT Announces The V100 Server-Class RISC-V Processor

Following the interesting SpacemiT K3 RVA23 RISC-V SoC, SpacemiT today announced the V100 server-class RISC-V processor.

(www.phoronix.com)